This invention relates to the field of semiconductor non-volatile memories, and, more particularly, to a memory of the Flash EEPROM type. Additionally, the invention relates to a method of reading data from an integrated electronic memory device which includes at least one non-volatile memory matrix. The invention also relates to a reading circuit for an integrated electronic non-volatile memory device on a semiconductor.
As is well known in the art, today""s microprocessors and microcontrollers require data to be input at ever higher rates, exceeding the limits of conventional memory technologies. The manufacturers of semiconductor memory devices are developing progressively faster memory architectures to improve the speed of memories. One of these techniques is the synchronous burst read mode. The burst read mode allows a microprocessor to read data from a memory at a faster rate than the customary random read mode.
At first, the microprocessor supplies only the memory address to the memory. The microprocessor then delivers a clock signal and, further to a reading at a random access time, the data is delivered from the memory at each rising edge of the clock signal. The next addresses are generated internally by the memory device. The frequency of the clock signal may be much higher than that of the random read signal. Thus, the data transfer rate can be substantially increased.
Current semiconductor non-volatile memory devices can support the random read mode, which is asynchronous, as well as the burst read mode, which is synchronous. The standard read mode is, however, the random mode. Two different constructions are commonly used to enable burst reading. A first prior art solution uses a sequence of enable control signals. To operate in the burst read mode, the memory device is provided with three additional control pins. These control pins may be used to interface a wide range of microprocessors. The control pins are generally designated LBA (Load Burst Address), BAA (Burst Address Advance), and CLK (Clock).
The burst read mode includes an addressing step and a corresponding data step. During the addressing step, the pin LBA must be held low for one clock period. On the rising edge of the clock signal, the starting address of the burst mode is loaded into an internal counter of an address bus. During the data step, the first available data of the burst mode becomes accessible an access time tACC after the rising edge of the clock signal. For the next data, the signal at the pin BAA is activated, and the rising edge of the clock signal at the pin CLK will increase the count in the counter and supply the remaining data in the appropriate sequence within the specific access time tBACC. The data sequence is supplied through the duration of the signal at the pin BAA.
A graph of some signals of a memory device operated in the burst read mode previously described plotted against a common time base is shown in FIG. 1. This first approach has a drawback in that once the memory has entered the burst read mode, only this mode is permitted. Thus, to return to the random read mode, another control sequence must be provided or the configuration register re-initialized.
A second prior approach includes writing into a configuration register incorporated into the memory device. This approach is described in U.S. Pat. No. 5,903,496, for example. This second approach is even more elaborate than the first, since the burst order, the clock signal frequency, and the burst length are fixed. Thus, to change any of these values, the configuration register must be re-written.
An object of the present invention is to implement read operations in the burst mode and involving no specific control sequences or register writing steps.
Another object of the present invention is to provide a non-volatile memory device with such structural and functional features to allow read operations in the burst mode with auto-sensing features.
Yet another object of the invention is to allow read operations in the auto-sensing burst mode to be carried out with no depth limits, and thereby to obtain a substantially continuous burst.
The concept behind this invention is to supply the memory with a clock signal at the same time a pulse is imposed on a signal to acknowledge the presence of an address to be read so that the pulse will encompass at least one rising edge of the clock signal. In this way, the starting read address will be the valid one at the time when the acknowledge pulse is received.
According to the invention, a method of reading data from an electronic integrated memory device including at least one non-volatile memory matrix includes supplying the memory device with an address of a memory location from which a reading is to be taken, accessing the memory matrix in a random read mode, supplying the memory device with a clock signal and an address acknowledge signal, detecting a request for read accessing in a burst mode, and starting a burst reading responsive to a rising edge of the clock signal. More specifically, the burst reading may include reading plural memory words in parallel during a single period of the clock signal. The plural memory words may be addressed sequentially to be output from the memory device, and a new reading may be performed at a next address of a memory location during a time required to output the plural memory words. An address of the memory location may be registered at a rising edge of the address acknowledge signal. Furthermore, the address of the memory location is updated automatically for a next reading.
A read control circuit according to the present invention for a semiconductor-integrated electronic memory device including a non-volatile memory matrix is also provided. The read control circuit may include a row decoder connected to the memory matrix, a column decoder connected to the memory matrix, an address counter having respective outputs connected to the row decoder and the column decoder, and an address transition detect circuit for detecting an input transaction during an accessing step of the memory device. A plurality of read amplifiers may be connected to the column decoder and a plurality of registers may be associated with the plurality of read amplifiers for outputting data read from the memory matrix. Furthermore, the read control circuit may include a detection circuit receiving a clock signal and a burst read mode enable logic signal, a burst read mode control logic circuit connected to an output of the detection circuit, and a control logic circuit connected to an output of the address transition detect circuit and connected to the burst read mode control logic circuit. The control logic circuit may control random accessing of the memory matrix and be activated for reading from a memory address upon receiving a rising edge of the clock signal.